Power MOSFETs

Next Generation TrenchFET^® Technology Lowers On-Resistance Down to 0.00135 Ω at V_GS = 4.5 V

• TrenchFET Gen IV optimizes several key specifications:
• Max R_DS(on) down to 0.00135 Ω at V_GS = 4.5 V, down to
  0.001 Ω at V_GS = 10 V
• Very low Q_GD and exceptionally low Q_GD / Q_GS ratio: < 0.5
• Q_GD / Q_GS ratio down to 0.3
• Improved immunity to C_dV/dt gate coupling
• 25 to 30 V
• Package options include:
• Thermally advanced PowerPAK^® SO-8
• Thermally advanced PowerPAK 1212-8, about 1/3 the footprint
  area of SO-8

600 V and 650 V High Performance Super Junction MOSFETs

• 30 % reduction in conduction losses
• Increased power density and higher efficiencies
• On-resistance down to 43 mΩ
• Available in all standard TO packages

High-Performance 40 V to 150 V Power MOSFETs

• Next-generation technology provides very low on-resistance and ultra-low figure of merit (FOM) for 40 V to 150 V power MOSFETs
• Include industry's lowest on-resistance and FOM for 4.5 V rated devices
• Thermally advanced PowerPAK® packaging

Breakthrough P-Channel Technology Dramatically Cuts R_DS(on)

• Lowest on-resistance per area achieved for a p-channel provides on-resistance down to half of previous industry best
• Down to sub 2 mΩ in SO-8 footprint area
• Variety of package sizes, from PowerPAK SO-8 down to 1.6 mm x 1.6 mm PowerPAK SC-75 and 1.5 mm x 1 mm chipscale MICRO FOOT^®
• Low conduction losses save power in battery operated systems

Dedicated Automotive Process Reduces Defects

• Process design optimized for automotive excellence
• AEC-Q101 qualified; temperature ranges up to 175 °C
• Low on-resistance n- and p-channel Trench technologies
• Includes innovative space-saving package options

MOSFET FEA Thermal Simulation Tool

• Save simulations for further use and modifications
• Modeling for MOSFETs can include effect of other heat dissipating components
• Setups include: power profile, heat sink, PCB, system temp., air flow and more
• PDF report supplied with thermal images and temp data downloadable to Excel

Co-packaged MOSFETs reduce space while still obtaining low on-resistance and high current comparable to two discretes

• High- and low-side MOSFETs in one compact package
• On-resistance down to 3 mΩ
• Maximum current up to 30 A
• Three size choices
• 3 mm x 3 mm
• 6 mm x 3.7 mm
• 6 mm x 5 mm
• Lowers solution space and cost over two discrete MOSFETs, saving clearance and labeling space between them
• Simplifies layout
• Reduces parasitic inductance from PCB traces, increasing efficiency and reducing ringing

Integrated MOSFET and Schottky Diode Solution Increases Efficiency

• Both components on one monolithic chip reduces on-resistance
• Reduces body diode power losses
• Eliminates external Schottky diode for space and solution cost savings
• Ideal low-side switch for synchronous rectification

PolarPAK^® Brings Standard Packaging to Double-Sided Cooling

• Dual heat dissipation paths double current density (> 60 A)
• Standard packaging provides better die protection, reliability and easier manufacturing handling
• 20 V to 200 V devices
• Fixed footprint and pad layout across family, ≤ 100 V and ≥ 150 V
• Licensed by multiple sources

Replaces TSOP-6 and SO-8 MOSFETs for lower thermal resistance and smaller footprints

• Compact 3 mm by 1.8 mm footprint
• 3 W maximum power dissipation
• Single, dual, co-packaged n- and p-channel and MOSFET + Schottky versions
• Breakdown voltage ratings from 8 V to 20 V for p-channel and 20 V to 60 V for n-channel

OR-ing Power MOSFETs

• 20 V V_DS / 20 V V_GS
• Industry-lowest on-resistance in three SO-8 footprint package options
• Up to 36 % lower on-resistance for 20 V in SO-8 footprint area
• 1.6 mΩ for double-sided cooling in air-flow applications
• 2.4 mΩ for optimum heat dissipation in still air
• 2.8 mΩ in standard SO-8 package

Industry-First MOSFETs with On-Resistance Rated at V_GS = 1.2 V

• Optimized for use with the low-voltage core ICs
• Allow the driver voltage to turn on the switch from a lower output voltage
  than 1.8 V
• Help reduce power consumption and increase battery usage time
• Single n- and p-channel device options
• Footprints as small as 0.8 mm x 0.8 mm

2 mm x 2 mm Footprint Area is 50% that of the TSOP-6

• Comparable on-resistance: N-channel down to 11 mΩ, P-channel down to 16 mΩ
• Slim 0.6 mm profile is 40 % smaller than TSOP-6
• 75 % higher maximum power dissipation
• Includes devices with on-resistance ratings down to 1.2 V

Ultra-Low On-Resistance and Size

• PowerPAK SC-75 provides same 1.6 mm x 1.6 mm footprint as standard SC-75, but much lower on-resistance
• N-channel R_DS(on) as low as 0.020 Ω
• P-channel R_DS(on) as low as 0.027 Ω
• Ultra-thin profile, down to 0.6 mm
• Single and dual n- and p-channel versions available, including devices with on-resistance ratings down to 1.2 V
• Gives designers ultra-low on-resistance and ultra-small size in one device for saving power in space-constrained handheld applications

Industry's Smallest MOSFETs, Lowest On-Resistance for Chipscale Packaging

• Footprints of 1.5 mm x 1 mm, 1.2 mm x 1 mm, 1 mm x 1 mm, and 0.8 mm x
  0.8 mm
• Smallest height of 0.4 mm
• Low on-resistance for form factor
• Help reduce power consumption and increase battery usage time